Pipelining is a technique used in chip design that allows data propagation through processing stages or blocks. In general, processing blocks in a pipeline operate on clock pulses to communicate data between the blocks. However, clocking in and of itself consumes power. As a consequence, processing blocks in a pipeline waste power when clock pulses occur but the processing blocks do not process data on those clock pulses. On the other hand, decreasing clock rates increases the latency and limits maximum performance.
During operation of a pipeline, some blocks may be more loaded than others. For example, an error correction processing block in a pipeline may become more heavily loaded if the numbers of errors it has to correct is very high, while other blocks in the pipeline do not have as much work to do. If the clock rate remains fixed for these less heavily-loaded blocks, clock pulses may be wasted, resulting in the processing blocks needlessly consuming power.